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NB4N441MNGEVB
hold timing to the respective SCLOCK rising
edge as specified in the AC Characteristics
section of the datasheet document. The MOST
Significant Bit (MSB), P4, is indexed in first
followed by P3, P2, P1, N2, N1, N0, M9
through the LEAST Significant Bit (LSB),
M0, indexed in last. A Pulse on the SLOAD
pin after the SHIFT register is fully indexed
(18 clocks) will load and latch the data values
for the internal P, M, and N registers. The
SLOAD pulse Low to HIGH rising edge
transition transfers the data from the SHIFT
register to the LATCH register. The SLOAD
Pulse HIGH to LOW transition will lock the
new data values into the LATCH register.
5. Output Enable ON : Switch SW1 (DOWN) or
externally HIGH through J11 (offset LVCMOS/
LVTTL of 2.0V HIGH and ? 1.3 V LOW) to
enable the output after setup. LED D3 indicator
will be ON to indicate an enabled output.
ALTERNATE STEP 2: LAB SET ? UP PROCEDURE FOR
SINGLE SUPPLY (INTO HIGH IMPEDANCE PROBES)
1. Output Enable OFF : Switch SW1 (UP) or
externally LOW through J11 (standard LVCMOS/
LVTTL of 2.0V HIGH and 0.8 V LOW) to disable
the output during setup. LED D3 indicator will be
off to indicate disabled output.
2. Supplies : Connect a “single” power supply to the
evaluation board for 3.3 V operation as follows:
VCC (RED banana jack or clip anvil) at +3.3
V
SMAGND (YELLOW banana jack or clip
anvil) at 0 V
DUTGND (BLACK banana jack or clip anvil)
0V
3. Output : Connect LVPECL OUTPUT CLOCK and
OUTPUT CLOCK outputs to the oscilloscope
with matched cables. The device outputs will
require proper termination. A thevenin parallel
termination scheme can be accomplished by
populating Resistor Pads (R76, R77, R78, and
R79) provided on the OUTPUT CLOCK and
OUTPUT CLOCK lines near the SMA connectors.
Install 127 Ohm resistors R77 at SG4 and R78 at
SG5. Install 83 Ohm resistors R76 at SG2 and R79
at SG2. See AND8020 for additional details. Use
HIGH IMPEDANCE (FET) Probes or equipment
only. Do not use LOW IMPEDANCE (50 W )
equipment or probes when using thevenin parallel
termination or the signal will be double
terminated.
4. Trigger : Ensure the oscilloscope trigger input is
setup and adjusted properly. A self triggered
real ? time high impedance input scope will not
require an external trigger connection.
5. XTAL/CLK Input: Determine if the onboard
crystal or an external signal reference will be used.
Onboard Crystal signal source is default ready for
use.
NOTE: If an external clock reference is used, then
dismount crystal and connect a clock signal
(10 MHz ? 50 MHz) with standard
LVTTL/LVCMOS into INPUT CLOCK (J1). Also
short from the bottom side “through hole trace” of
INPUT CLOCK to J5 (not J3). Do not drive
XTAL2. Termination of the signal generator may
be needed with 50 W to SMA ground.
6. Program SDI: The P, M, and N internal registers
may be programmed by (A) the onboard PLD or
(B) by using the three line LVTTL/LVCMOS
Serial Data Interface (SDI) consisting of a
SERIAL DATA (SDATA) input, a SERIAL
CLOCK (SCLOCK) input, and a SERIAL LOAD
(SLOAD) as follows:
A. Onboard PLD
1. Insure all 4 of the J12 (441 CONFIG) jumpers
are all installed connecting the PLD output to
the Device
2. Insure JP1 LED/PLD indicates power is
applied to the PLD (LED on)
3. Insure J3 (external CLOCK line from J1) is
open, not LOADED, DRIVEN, or shorted;
4. Insure SW5 (LEFT: CUSTOM 441,
RIGHT:STANDARD 442) select is set to the
LEFT (bypassing SW2, SEL[3:0]. Note LED
will light for “CUSTOM FREQUENCIES”.
5. Set SW4, SW6, and SW7 rocker switches to
desired P, M, and N programming values:
UP =0 LOGIC LOW (LED indicator OFF);
DOWN = 1 LOGIC HIGH (LED indicator
ON).
6. Load program values by depressing
momentary switch SW8, or send a pulse
signal through J13 SMA connector (when
installed) with standard LVTTL/LVCMOS
levels.
B. External SDI
1. See datasheet DC Table, AC Table, as well as
Figures 5 and 6.
2. To use the SDI serial data input port, generate
and input SCLOCK, SDATA, and SLOAD
signals with standard LVTTL/LVCMOS
levels. The SCLOCK signal will sample the
information presented on SDATA line. Values
are loaded and indexed into a 18 bit shift
register. The register shifts once per rising
edge of the SCLOCK input. The serial input
SDATA bits must each meet setup and hold
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